Analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are increasingly being based on a sigma-delta (ΣΔ) architecture.
FIG. 1 illustrates a generalized architecture as used in a sigma delta analog-to-digital converter (ADC). An analog sigma-delta modulator 11 receives an analog input signal 10 and generates a high rate, low bitwidth, digital signal 12. This signal is applied to a digital decimation stage 13 which converts the signal to a low rate, high bitwidth, digital signal 14. The sigma-delta modulator 11 can be a single bit or multi-bit modulator.
FIG. 2 illustrates a generalized architecture as used in a sigma-delta digital-to-analog converter (DAC). A digital interpolation stage 21 receives an input digital signal 20 having a low rate and high bitwidth. The interpolation stage 21 generates a signal 22 having a high rate and high bitwidth by interpolating, i.e. calculating new samples to fit between the samples of the incoming digital signal. The interpolated signal 22 is applied to a digital sigma-delta modulator 23. The signal 24 output by the modulator 23 has a high rate and low bitwidth. Signal 24 is applied to a digital-to-analog conversion stage 25 which includes low pass filtering (not shown) to provide a smoothed analog output signal 26.
Conventionally interpolation (for sigma-delta DACs) and decimation (for sigma-delta ADCs) are each executed in different stages: one hardware structure for high conversion rate (typically 8 or 16), and one or more DSP controlled digital Finite Impulse Response (FIR) filters for high quality but a lower conversion rate (typically conversion rate of 2 on each filter). Optimised interpolation and decimation FIR processes are conventionally performed by separate DSP engines, each engine being optimised for one of the processes, since many of the optimisations seem incompatible between processes. Often, in digital signal processing applications such as audio codecs, there is a requirement for both an ADC and a DAC. Providing two separate, optimised, DSP engines for the decimation and interpolation processes incurs the penalties of requiring increased die space on an integrated circuit, increased cost and increased power requirements.
Accordingly, the present invention seeks to more efficiently provide a decimation and an interpolation function.